Technically, Moore's Law relates to the cost curve for any given complexity, not necessarily the transistor count. That is, that the most efficient point of marginal cost/marginal performance approximately doubles every two years (implicitly, as the node shrinks).

The concern people have is that each node shrink isn't delivering the same benefits as before... But is that true, or is the node-to-node cadence just rising? I pose that the shrinking cadence is simply a problem of lack of funding to the big fabs, not one of the technology becoming intrinsically infeasible.

In particular, I'd like to point out that the switch from planar to FinFET was also largely driven by the planar technology becoming rather infeasible for scaling at that time - we should see a similar transition to GAAFET soon and I'm tentatively hopeful for TSMC's future GAAFET node densities after they ship N2 (which, itself, is barely a node shrink so much as it is a technology demonstrator).

Unless China can co-develop the EUV machine with the node itself, they will be very very late to this gap in foundry capability. If they can, they will only be very late.