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50 million rendered polygons vs one spicy 4.2MB boi
(lemmy.world)
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this post was submitted on 14 May 2024
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Both ARM and RISC-V have compressed instructions. Dunno how ARM works but with RISC-V the 16-bit instruction set is freely interspersable with the 32 bit one, which also get their alignment reduced to 16 bits. Gets like 95% of the space reduction possible with full variable-width instructions without overcomplicating the insn decoder.
As to addressing and loads and arithmetic: No such instructions, but every CPU but the tiniest ones are expected to do macro-op fusion for things like indexed loads. Here's an overview.
The MMU thing... well the vector extension can do gather/scatter, I guess it could stay within the letter of "use the MMU once" but definitely not the spirit.