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The C++ learning process
(aussie.zone)
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this post was submitted on 02 Sep 2024
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I had to do a module programming in VHDL for my EE degree.
Every time I see it mentioned anywhere I have a compulsion to scream: FUCK VHDL AND ITS FUCKING ERRORS! NO YOUR ANALYSIS & SYNTHESIS IS UNSUCCESSFUL!
I did not pursue a career in electronics…
One of the key problems of learning VHDL at universities is that most teachers there are amazingly clueless about the language. Not only do you need a bit of a different mindset (you do not program, you define), but their knowledge of language and systems is stuck in the last century.
When I was a regular in a VHDL group on the site we don't mention here, we regularly had students who got taught techniques that are obsolete or at least deprecated since 1989.