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this post was submitted on 07 Oct 2023
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RISC-V is an architecture like ARM. What are you going to do, put a backdoor in the add instruction?
Exactly. An add instruction, or any instruction needs to be carried out in steps within the hardware. Sometimes there's systematic bugs in these implementations that can be exploited.
Plus, it's an open architecture where those bugs can be exposed and fixed. Where in Intel/arm based architectures, they can be rolled out to the world and be used by those in the know.
Eg: https://www.techrepublic.com/article/is-the-intel-management-engine-a-backdoor/
RISC-V being open doesn't mean all implementations using it have to be, though
There's nothing stopping a manufacturer from putting their own Intel Management Engine equivalent in a RISC-V CPU
You are correct. I though it was copyleft GPL something.
Thanks for bringing it into my attention. :)
The simplest risc-v implementations don't need microcode at all.
There's likely a lot of backdoors in x86 microcode.