AMD's 3D V-Cache, which is what I assume you're thinking of, is a clever but limited optimization that stacks memory on top of existing logic to give you more cache. Meanwhile, Huawei's Tau Scaling Law is a total rethinking of chip design where you actually fold the logic circuits themselves into multiple active layers to shrink the physical distance signals have to travel. This is a much bigger deal because it attacks the fundamental bottleneck of signal propagation delay rather than memory latency. The key advantage of Tau is that it does not require cutting edge EUV lithography to keep advancing transistor density. Huawei claims they can achieve 1.4nm equivalent densities by 2031 using older process nodes just by stacking logic vertically. AMD still needs TSMC's smallest transistors to stay competitive, but Tau architecture uses 3D folding to bypass the need for smaller transistors altogether.