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submitted 10 months ago by glibg10b@lemmy.ml to c/buildapc@lemmy.world

cross-posted from: https://lemmy.ml/post/9114359

My motherboard provides 4x USB 3.2 Gen1 ports for rear I/O and another 2x USB 3.2 Gen1 ports for front I/O (through the header), but my chipset only supports 2x USB 3.2 Gen1 ports. Where is the support for the other ports coming from?

Motherboard Wikipedia
Motherboard rear I/O: 2x USB 2.0 ports, 4x USB 3.2 Gen1 ports, 2x USB 3.2 Gen2 portsMotherboard headers: 4x USB 2.0 ports, 2x USB 3.2 Gen1 ports Wikipedia B450 chipset: 6x USB 2.0 ports, 2x USB 3.2 Gen1 ports, 2x USB 3.2 Gen2 ports

The motherboard is an ASRock B450M Steel Legend

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[-] SomeoneSomewhere@lemmy.nz 4 points 10 months ago

I think some of the USB ports come directly from the CPU, others come from the chipset. This allows the dirt-cheap A300 boards to operate with no chipset at all but still have a couple of USB ports, and likewise with laptops.

[-] Septimaeus@infosec.pub 3 points 10 months ago* (last edited 7 months ago)

Likely ~~SB~~ chipset but also, vendors sometimes use an extra 4 lanes of PCIe for miscellaneous additional unswitched I/O, including USB (which might be a useful expansion but otherwise just means fewer m.2 slots).

[-] glibg10b@lemmy.ml 2 points 10 months ago

Likely SB

Are you saying this motherboard likely has a southbridge?

[-] Septimaeus@infosec.pub 2 points 10 months ago* (last edited 10 months ago)

lol yes, right next to the IDE connector. Nah I meant from the chipset. Here’s the doodle from my mainboard manual for example.

aorus b650i chipset diagram

[-] glibg10b@lemmy.ml 2 points 10 months ago

Ah, so the chipset uses a few PCIe lanes from the CPU for some USB controllers, and the other USB controllers use dedicated USB lanes coming from the CPU?

[-] Septimaeus@infosec.pub 3 points 10 months ago

Right, the CPU has a number of standard I/O controllers onboard including USB. No PCIe lanes required for these IIRC. They live on the die itself, often adjacent to the PCIe controllers.

this post was submitted on 10 Dec 2023
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